By Topic

Self-assembled nanowire-on-insulator (SANOI) for nano-chip technology

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Bin Yu ; Center for Nanotechnol., NASA Ames Res. Center, Moffett Field, CA, USA ; G. Calebotta ; K. Yuan ; M. Meyyappan

One-dimensional semiconducting nanowires (Si or Ge) directly synthesized on insulator layer by chemical method provide a viable technology analogous to silicon-on-insulator (SOI) and germanium-on-insulator (GOI), yet presenting much better chip design/integration flexibility, structural scalability, and cost-effectiveness. The new technology, called self-assembled nanowire-on-insulator (SANOI), illustrates a good example of how bottom-up nanotechnology based on inexpensive chemistry may provide solution to some of the most daunting challenges in the conventional silicon CMOS scaling.

Published in:

5th IEEE Conference on Nanotechnology, 2005.

Date of Conference:

11-15 July 2005