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Dynamic zero-sensitivity scheme for low-power cache memories

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2 Author(s)
Yen-Jen Chang ; Dept. of Comput. Sci., Nat. Chung-Hsing Univ., Taichung, Taiwan ; Feipei Lai

A low-power cache has become essential in many applications, but cache accesses contribute significantly to a chip's total power consumption. Because most bit values read from the cache are 0's, the authors introduce a dynamic zero-sensitivity (DZS) scheme that reduces average cache power consumption by preventing bitlines from discharging in reading a 0.

Published in:

Micro, IEEE  (Volume:25 ,  Issue: 4 )

Date of Publication:

July-Aug. 2005

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