Referenced Items are not available for this document.
A 4.9 to 6.4 Gb/s 2-level SerDes ASIC I/O core designed in 0.13 μm CMOS uses a 4-tap FFE in the transmitter and a 5-tap DFE with receiver AGC. Error-free operation is achieved on channels with over 30 dB loss at the half-baud rate. The TXRX pair consumes 290 mW from a 1.2 V supply and uses a die area of 0.79 mm2.
Published in:
Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International
Date of Conference: 10-10 Feb. 2005
- Page(s):
- 62 - 585 Vol. 1
- ISSN :
- 0193-6530
- Print ISBN:
- 0-7803-8904-2
- INSPEC Accession Number:
- 8643459
- Conference Location :
- San Francisco, CA
- Digital Object Identifier :
- 10.1109/ISSCC.2005.1493869
- Product Type:
- Conference Publications
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