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Sea of Leads Compliant I/O Interconnect Process Integration for the Ultimate Enabling of Chips With Low- \hbox {k} Interlayer Dielectrics

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6 Author(s)
Bakir, M.S. ; Microelectron. Res. Center, Georgia Inst. of Technol., Atlanta, GA, USA ; Dang, B. ; Emery, R. ; Vandentop, G.
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Sea of leads (SoL) process integration for the series of steps required to transform a fully intact die at the wafer level to a die that is assembled onto a board is described. The primary goal is to address the issues involved in reconciling the fabrication and assembly requirements of compliant leads, such as SoL, with those of standard semiconductor processes and chip assembly techniques. The effort is motivated in-part by the potential failure of the low- \hbox {k} interlayer dielectric in microprocessors as a result of high mechanical stresses due to the coefficient of thermal expansion (CTE) mismatch between the chip and the board. SoL, and other compliant interconnections, mitigate this problem by mechanically decoupling the chip and the board. While compliant leads offer advantages over C4 technology, there is much to consider during the series of steps needed to transform the fully intact dice at the wafer level to dice that are assembled onto the board. The use of an encapsulation film over the leads during wafer sawing is shown to be necessary for slippery leads and other free-standing compliant leads. The use of a suitable flux when the leads are finished with a nickel–oxide nonwettable layer is essential for a successful wafer-level solder reflow. Successful die assembly using thermocompression bonding is demonstrated using two different SoL dice with correspondingly different substrates. The resistance of a chain of 30 cascaded leads is 2.7 \Omega .

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Advanced Packaging, IEEE Transactions on  (Volume:28 ,  Issue: 3 )