By Topic

A constraint length and throughput reconfigurable architecture for Viterbi decoders

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Obeid, A.M. ; Inst. of Microelectronic Syst., Darmstadt Univ. of Technol., Germany ; Garcia Ortiz, A. ; Glesner, M.

The use of dynamically reconfigurable architectures is particularly profitable when utilized in multi-standard systems. In this work, we propose a constraint length and throughput reconfigurable architecture for Viterbi decoders. Based on the Radix-2 single delay feedback architecture, we introduce an extension that can realize both the ACS and the trellis window unit of Viterbi decoders. The presented approach facilitates not only constraint length and throughput reconfigurability, but moreover, tradeoff between power consumption and decode quality. The proposed architecture can be easily reconfigured by adding or removing standard building blocks. Moreover, the techniques introduced here can be easily employed in any DSP application with a butterfly-like data flowgraph and therefore, can benefit the design of DSP coarse grain reconfigurable systems.

Published in:

Industrial Technology, 2004. IEEE ICIT '04. 2004 IEEE International Conference on  (Volume:3 )

Date of Conference:

8-10 Dec. 2004