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GaAs FET with a degenerate semiconductor gate

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4 Author(s)
Umemoto, Y. ; Hitachi, Ltd., Tokyo, Japan ; Takahashi, S. ; Ono, Y. ; Hashimoto, N.

A new GaAs FET structure has been proposed and examined experimentally in which the gate material is degenerate p-Al0.3Ga0.7As fabricated directly on to a p-type layer of undoped semi-insulating GaAs substrates. Obtained transconductance was 207mS/mm under the gate bias of 2V for the gate length of 2\\mu m and the onset voltage of the gate leakage current was 0.5-0. 6V higher than that of MESFETs. These characteristics were explained by the presence of an n-type inversion layer located at p-AlGaAs/p-GaAs interface. Temperature dependence of the drain current leads to a conclusion that the Fermi level was pinned at the interface states 0.475eV above the valence band.

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Electron Devices Meeting, 1985 International  (Volume:31 )

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