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A new full CMOS SRAM cell structure that can reduce the cell size to about a half of the conventional one, is presented. The cell structure is featured with such technologies as p/n polycide gate electrodes, shallow trench isolation, deep trench isolation and double level Al interconnects. Cell size measuring 7.4 × 14.1 µm (=104.34 µm2), has been achieved experimentally, which is about a half of the conventional one of the same design rule (1.2 µm). A test vehicle with a 4 Kb cell array was fabricated and its electrical characteristics were examined. Any appreciable degradations in the SRAM operation items were not observed. With this new cell structure, cell occupied area of 27.35 mm2is expected to be realized in 256 Kb full CMOS SRAM.