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A merged CMOS/bipolar VLSI process

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2 Author(s)
F. Walczyk ; Digital Equipment Corporation, Hudson, Ma. ; J. Rubinstein

Presented are the results of a merged CMOS/bipolar process used to implement circuit structures using both fully isolated bipolar transistors with low collector series resistance and CMOS transistors. Latch-up suppression and effective bipolar performance are simultaneously achieved by the combined use of an n+ buried layer, epitaxial processing and a tailored base ion implant. A merged CMOS/bipolar buffer circuit is described and measured results are shown.

Published in:

Electron Devices Meeting, 1983 International  (Volume:29 )

Date of Conference: