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A new self-aligned transistor structure suitable for high-speed and low-power bipolar LSI's has been developed. The transistor, which has one or submicron emitter geometry, a non-LOCOS oxide isolation and a polysilicon base contact, is fabricated by selective growth of poly- and single-crystalline silicon and by subsequent self-aligned process. The fully self-aligned transistor structure results in substantial reduction of parasitic capacitances and resistances without fine lithography. The self-aligned transistors were evaluated using 39-stage LCML ring-oscillators designed with 2.5 micron design rules. Typical per-stage delays were 190 ps at 0.22 mW/gate and 83 ps at 1.0 mW/gate.