By Topic

A new complementary transistor structure for analog integrated circuits

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Kikkawa, T. ; Nippon Electric Co., Ltd., Kawasaki City, Japan ; Suganuma, T. ; Tanaka, K. ; Hara, T.

A new complementary transistor structure has been developed. This paper presents a new technique which provides a fully complementary transistor structure for analog integrated circuits. The pnp transistor is fabricated by triple diffusion process in n type epitaxial layer on p type substrate, and is isolated from the substrate by inserting n- ion implanted layer between p+ collector buried layer and the substrate. This technique results in 5 to 10 times improvement in gain bandwidth product fT, maximum collector current IC(max)and collector saturation voltage VCE(sat)in comparison with conventional pnp transistors. Consequently, a fully complementary pnp transistor to npn transistors can be obtained.

Published in:

Electron Devices Meeting, 1980 International  (Volume:26 )

Date of Conference: