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Limiting factors for programming EPROM of reduced dimensions

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4 Author(s)
M. Wada ; Toshiba Corporation, Kawasaki, Japan ; S. Mimura ; H. Nihira ; H. Iizuka

In order to realize high density EPROM's it is necessary to reduce the dimensions of EPROM cells. In this paper the programming characteristics of the floating gate EPROM's are discussed in relation to the limiting factors for device parameters and the programming conditions. Some problems which arise from the arrayed cell configuration are clarified. The programming speed of an EPROM is remarkably lowered by the voltage drop in a bit line due to an excess current flow through deselected cells which is induced by pulling up of the floating gate potential due to capacitance coupling between the bit line and the floating gate. A punch-through current in memory cells has the same effect on the programming characteristics. The feasibility of higher density EPROM's are also discussed by taking these problems into account.

Published in:

Electron Devices Meeting, 1980 International  (Volume:26 )

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