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Global routing techniques for an automatic mixed analog/digital IC layout compiler

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1 Author(s)
Lin, Z.-M. ; Dept. of Electr. Eng., Maryland Univ., College Park, MD, USA

Global routing techniques for an automated analog/digital IC layout compiler are presented. The global router routes in a net-by-net, high-sensitivity-net-first order. Minimum trees are searched for the interconnection of sensitive nets and power nets. For the routing of noise nets, the router provides a net-crossing-free terminal assignment between sensitive nets and noise nets for the routing of channels. Efficient terminal assignment and extraction techniques for the router are also presented

Published in:
Southeastcon '91., IEEE Proceedings of

Date of Conference: 7-10 Apr 1991

Page(s):
392 - 396 vol.1
Meeting Date :
07 Apr 1991-10 Apr 1991
Print ISBN:
0-7803-0033-5
INSPEC Accession Number:
4076512
Conference Location :
Williamsburg, VA
Digital Object Identifier :
10.1109/SECON.1991.147780

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