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14-bit, 2.2MS/s sigma delta ADCs

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16 Author(s)
Morizio, J. ; Mitsubishi Electric America, Durham, NC ; Hoke, M. ; Kocak, T. ; Geddie, C.
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This paper presents the design and test results of a 4th and 6th order, 14-bit, 2.2MS/s sigma-delta ADC. The analog modulator and digital decimator sections were implemented in a .35µM CMOS, double poly, triple level metal 3.3v process. The design objectives for these ADCs was to achieve 85dB SNDR with less than 200mW power dissipation.

Published in:

Solid-State Circuits Conference, 1999. ESSCIRC '99. Proceedings of the 25th European

Date of Conference:

21-23 Sept. 1999

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