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A CMOS attenuator with wide dynamic range has been designed and fabricated in a 0.13μm CMOS process. The design employs two nonidentical cascaded T-stages that are activated consecutively to improve linearity. The design operates in the frequency band of DC-2.5GHz with 0.9-3.5dB insertion loss and 42dB maximum attenuation in the entire frequency range. Worst case SII is -8.2dB across the frequency band. The design achieves an IIP3 of +20 dBm at mid-attenuation.
Published in:
VLSI Circuits, 2005. Digest of Technical Papers. 2005 Symposium on
Date of Conference: 16-18 June 2005
- Page(s):
- 90 - 93
- Print ISBN:
- 4-900784-01-X
- INSPEC Accession Number:
- 8573471
- Digital Object Identifier :
- 10.1109/VLSIC.2005.1469341
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