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Soft errors are changes in logic state of a circuit/system resulting from the latching of single-event transients (transient voltage fluctuations at a logic node or SETs) caused by high-energy particle strikes or electrical noise. Due to technology scaling and reduced supply voltages, they are expected to increase by several orders of magnitude in logic circuits. In this work, we present a very efficient and systematic approach to cope with soft errors in combinational and sequential logic circuits. The features and merits of our approach are: (1) use of error masking in non-critical paths along with error detection and recovery in critical paths, which substantially lowers overhead for error correction; (2) average 93% soft-error rate (SER) reduction as SETs of width approximately half the clock period time can be tolerated; (3) area and power overheads can be traded-off with SER reduction based on application requirements. We also present two additional techniques to more aggressively utilize slack in circuits and further improve SER reduction by: (1) exploiting circuit delay dependence on input vectors and (2) redistributing slack in pipelined circuits.