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An advanced bit-line clamping scheme in magnetic RAM for wide sensing margin

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4 Author(s)
Jong-Chul Lim ; Dept. of Electron. Eng., Korea Univ., Seoul, South Korea ; Hye-Seung Yu ; Jae-Suk Choi ; Soo-Won Kim

This paper proposes the bit-line clamping scheme for a stable signal margin in magnetoresistance RAM. MRAM distinguishes data by the difference of resistance in MTJ. However, there are so many error sources in MTJ that it limits a yield factor. In this paper, we focus on the resistance variation due to bit-line voltage. For maximum signal difference, we try to reduce bit-line voltage as low as possible. Proposed scheme employs CBLSA, equalizer transistor and 1T1MTJ array structure. This method has very excellent bit-line clamping characteristic and overall memory can be designed a simple architecture using current mode sensing. As a result, proposed memory structure can clamp a bit-line voltage under 0.15V and it uses very small power and area. This lower bit-line voltage promises more stable data accessing in MRAM. The circuit is designed in a 0.35μm-CMOS technology.

Published in:

Design Automation Conference, 2005. Proceedings of the ASP-DAC 2005. Asia and South Pacific  (Volume:2 )

Date of Conference:

18-21 Jan. 2005

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