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A systematic framework for high throughput MAP decoder VLSI architectures

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3 Author(s)
M. Elassal ; Center for Adv. Comput. Studies, Univ. of Louisiana, Lafayette, LA, USA ; A. Kumar ; M. Bayoumi

The paper presents a systematic method for the development of high throughput MAP decoder architectures. High throughput is achieved by exploiting more algorithmic parallelism. The paper proposes the use of the trellis-time graph to study the parallel MAP decoder architectures analytically. A parameterized windowing approach is developed to construct the trellis-time graph of the decoding operation. Next, an exhaustive search is used to explore the parallelism vs. hardware resources systematically. This method is applied towards the design of a MAP decoder that has a frame of size 320 bits. A tradeoff among the decoding delay, number of kernels, number of BMM banks, and number of SMM banks is presented.

Published in:

2005 IEEE International Symposium on Circuits and Systems

Date of Conference:

23-26 May 2005