Referenced Items are not available for this document.
Computationally very expensive dynamic-programming matching of data sequences has been directly implemented in a fully-parallel-architecture VLSI chip. The circuit operates as digital logic in the signal domain, while analog processing is carried out in the time domain based on the delay-encoding-logic scheme. As a result, a high-speed low-power best-match-sequence search has been established with a small chip area. The typical matching time of 80 ns with the power dissipation of 2 mW has been demonstrated with fabricated prototype chips.
Published in:
Solid-State Circuits, IEEE Journal of
(Volume:40
,
Issue:
7
)
Date of Publication: July 2005
- Page(s):
- 1578 - 1582
- ISSN :
- 0018-9200
- INSPEC Accession Number:
- 8525225
- Digital Object Identifier :
- 10.1109/JSSC.2005.847214
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 27 June 2005
- Issue Date :
- July 2005
- Sponsored by :
- IEEE Solid-State Circuits Society
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