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A delay-encoding-logic array processor for dynamic-programming matching of data sequences

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2 Author(s)
Ogawa, M. ; Dept. of Frontier Informatics, Univ. of Tokyo, Japan ; Shibata, T.

Computationally very expensive dynamic-programming matching of data sequences has been directly implemented in a fully-parallel-architecture VLSI chip. The circuit operates as digital logic in the signal domain, while analog processing is carried out in the time domain based on the delay-encoding-logic scheme. As a result, a high-speed low-power best-match-sequence search has been established with a small chip area. The typical matching time of 80 ns with the power dissipation of 2 mW has been demonstrated with fabricated prototype chips.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:40 ,  Issue: 7 )