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A 6-bit 1.2-GS/s low-power flash-ADC in 0.13-μm digital CMOS

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5 Author(s)
Sandner, C. ; Dev. Center Villach, Infineon Technol. Austria, Villach, Austria ; Clara, M. ; Santner, A. ; Hartig, T.
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We present a 6-bit 1.2-GS/s flash-ADC with wide analog bandwidth and low power, realized in a standard digital 0.13 μm CMOS copper technology. Employing capacitive interpolation gives various advantages when designing for low power: no need for a reference resistor ladder, implicit sample-and-hold operation, no edge effects in the interpolation network (as compared to resistive interpolation), and a very low input capacitance of only 400 fF, which leads to an easily drivable analog converter interface. Operating at 1.2 GS/s the ADC achieves an effective resolution bandwidth (ERBW) of 700 MHz, while consuming 160 mW of power. At 600 MS/s we achieve an ERBW of 600 MHz with only 90 mW power consumption, both from a 1.5 V supply. This corresponds to outstanding figure-of-merit numbers (FoM) of 2.2 and 1.5 pJ/convstep, respectively. The module area is 0.12 mm2.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:40 ,  Issue: 7 )

Date of Publication:

July 2005

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