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Asynchronous on-chip networks

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5 Author(s)
M. Amde ; Dept. of Electr. & Comput. Eng., Univ. of California, San Diego, CA, USA ; T. Felicijan ; A. Efthymiou ; D. Edwards
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Various kinds of asynchronous interconnect and synchronisation mechanisms are being proposed for designing low power, low emission and high-speed SOCs. They facilitate modular design and possess greater resilience to fabrication time inter-chip and run-time intra-chip process variability. They can provide a solution for low power consumption in chips and simplify global timing assumptions, e.g. on clock skew, by having asynchronous communication between modules. A few methodologies, including globally asynchronous, locally synchronous and desynchronisation, aim at leveraging the benefits of both synchronous and asynchronous design paradigms. The authors survey various methodologies used for leveraging asynchronous on-chip communication. They investigate various GALS based implementations, desynchronisation strategies and asynchronous network-on-chip (NoC) designs.

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IEE Proceedings - Computers and Digital Techniques  (Volume:152 ,  Issue: 2 )