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In low-power design for deep submicrometer and nanometer regimes, peak power, power fluctuation, average power, and total energy are equally important design constraints. In this paper, we propose datapath scheduling algorithms for simultaneous minimization of peak and average power. The minimization schemes based on integer linear programming are developed for the design of datapaths that can function in three modes of operation: 1) single supply voltage and single frequency; 2) multiple supply voltages and dynamic frequency clocking (MVDFC); and 3) multiple supply voltages and multicycling. The techniques are evaluated by estimating the peak power consumption, the average power consumption and the power delay product of selected high level synthesis benchmark circuits for different resource constraints. Experimental results indicate that combining multiple voltages and dynamic frequency clocking as in the MVDFC scheme, yields significant reductions in the peak power, the average power, and the power delay product.