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Design of a power-reduction Viterbi decoder for WLAN applications

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4 Author(s)
Chien-Ching Lin ; Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan ; Yen-Hsu Shih ; Hsie-Chia Chang ; Chen-Yi Lee

In this paper, a 64-state four-bit soft-decision Viterbi decoder with power saving mechanism for high speed wireless local area network applications is presented. Based on path merging and prediction techniques, a survivor memory unit with hierarchical memory design is proposed to reduce memory access operations. It is found that more than 70% memory access can be reduced by taking advantage of locality. Moreover, a low complexity compare-select-add unit is also presented, leading to save 15% area and 14.3% power dissipation as compared to conventional add-compare-select design. A test chip has been designed and implemented in 0.18-μm standard CMOS process. The test results show that 30∼40% power dissipation can be reduced, and the power efficiency reaches 0.75 mW per Mb/s at 6 Mb/s and 1.26 mW per Mb/s at 54 Mb/s as specified in IEEE 802.11a.

Published in:

IEEE Transactions on Circuits and Systems I: Regular Papers  (Volume:52 ,  Issue: 6 )