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Characterizing the effects of the PLL jitter due to substrate noise in discrete-time delta-sigma modulators

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1 Author(s)
P. Heydari ; Dept. of Electr. Eng. & Comput. Sci., Univ. of California, Irvine, CA, USA

This paper investigates the impact of clock jitter induced by substrate noise on the performance of the oversampling ΔΣ modulators. First, a new stochastic model for substrate noise is proposed. This model is then utilized to study the clock jitter in clock generators incorporating phase-locked loops (PLLs). Next, the effect of the clock jitter on the performance of the ΔΣ modulator is studied. It will be shown that substrate noise degrades the signal-to-noise ratio of the ΔΣ modulator while the noise shaping does not have any effect on clock jitter induced by substrate noise. To verify the analysis experimentally, a circuit consisting of a second-order ΔΣ modulator, a charge-pump PLL, and forty multistage digital tapered inverters driving 1-pF capacitors is designed in a 0.25-μm standard CMOS process. Several experiments on the designed circuit demonstrate the high accuracy of the proposed analytical models.

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IEEE Transactions on Circuits and Systems I: Regular Papers  (Volume:52 ,  Issue: 6 )