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A generic CAD tool for efficient NoC design

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3 Author(s)
Evain, S. ; Univ. de Bretagne Sud, Lorient, France ; Diguet, J.-P. ; Houzet, D.

Network on chip (NoC) using packet switching is a solution to cope with complex system on chip (SoC) communications. However, tools are needed to help designers to deal with NoC. The two elements composing an NoC are its routers and its network interfaces (NI). We focus on the specification and generation steps of the μspider NOC design flow that addresses what we consider as the main features of a realistic and useful NoC. Firstly, the synthesis tool is based on a generic router through a user friendly design interface. Secondly, it supports the management of different levels of quality of service (QoS), allowing a guaranteed throughput (GT) service in addition to a classical best effort (BE) service. Finally, it can be tuned to handle asynchronous communications. The paper presents the router architecture and its various custom characteristics. We show the tradeoff between a hierarchical QoS channel implementation and the performance of the system.

Published in:

Intelligent Signal Processing and Communication Systems, 2004. ISPACS 2004. Proceedings of 2004 International Symposium on

Date of Conference:

18-19 Nov. 2004