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High yield, high uniformity, high performance 50 nm T-gate In0.52Al0.48As/In0.70Ga0.30As HEMT process

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4 Author(s)
Xin Cao ; Dept. of Electron. & Electr. Eng., Glasgow Univ., UK ; Thoms, S. ; Stanley, C. ; Thayne, I.

50 nm T-gates InP high electron mobility transistors (HEMTs) with a 70% indium channel were fabricated using a very robust fabrication process based on a novel UVIII/LOR/PMMA resist stack e-beam lithograph technology and on a "digital" gate recess technology. A typical device exhibited a gm of 1400 mS/mm and an ft of 420 GHz. A source and drain saturation current (IDSS) uniformity of 40 A/mm, a threshold voltage uniformity of 10 mV and a functional yield of 96% were also achieved.

Published in:

Solid-State and Integrated Circuits Technology, 2004. Proceedings. 7th International Conference on  (Volume:3 )

Date of Conference:

18-21 Oct. 2004

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