High yield, high uniformity, high performance 50 nm T-gate In/sub 0.52/Al/sub 0.48/As/In/sub 0.70/Ga/sub 0.30/As HEMT process

50 nm T-gates InP high electron mobility transistors (HEMTs) with a 70% indium channel were fabricated using a very robust fabrication process based on a novel UVIII/LOR/PMMA resist stack e-beam lithograph technology and on a "digital" gate recess technology. A typical device exhibited a g/sub m/ of 1400 mS/mm and an f/sub t/ of 420 GHz. A source and drain saturation current (I/sub DSS/) uniformity of 40 A/mm, a threshold voltage uniformity of 10 mV and a functional yield of 96% were also achieved.