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An IEEE-754 compliant, single and double precision floating-point (FP) adder for 14 FP operations is presented. FP operations, including addition, subtraction, conversion, comparison and the final addition and rounding of multiplication, have similar operation steps and are implemented in the FP adder. These operations are implemented based on a modified two-path FP addition that is altered in method of use and path separation criterion. In order to incorporate all these operations in the FP adder, it is necessary to select one suitable path for the operation first. Then the operation is perform in the selected path. The power dissipation is largely reduced by disabling the unselected path. The path separation criterion is also modified to ensure that only one path is selected for each operation case and the CLOSE path can be simplified. The FP adder is 3-stage pipelined and can execute an instruction every cycle.
Solid-State and Integrated Circuits Technology, 2004. Proceedings. 7th International Conference on (Volume:3 )
Date of Conference: 18-21 Oct. 2004