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Network on chip (NoC) is a new paradigm for designing IP core based systems on chip, which supports high degree of reusability and is scalable and re-configurable. In this paper, an efficient two-step genetic algorithm based design tool is described to map multimedia applications, which are abstracted by a parameterized multi-task-graph, onto a NoC architecture. In order to provide sufficient testing data, we developed an input data generation tool, which can generate a NoC backbone and random multi-task-graph test patterns. Experiments show that the two-step genetic algorithm tool can usually give reasonable design results within half a minute on a PC platform. The input data generation tool can also be used as a random task graph generation tool for general purposes.