Bipartition for 2.5-D floorplanning based on corner block list representation

This paper investigates a 3D die-stacking based VLSI integration strategy, so-called 2.5D integration, which can potentially overcome many problems stumbling the development system-on-chip (SoC), such as interconnect delay of monolithic problems due to scaling and increasing chip area. We present an approach using bipartitioning for 2.5D floorplanning based on corner block list representation. Experimental results show significant wirelength reduction compared to monolithic floorplanning.