VLSI implementation of fast Fourier transformation for OFDM-based high-speed wireless applications

In this paper, we introduce a fixed-point 16-bit 64 point FFT processor architecture for OFDM-based wireless applications. The processor is based on the DIT (decimation-in-time) radix-2 butterfly FFT algorithm. A canonical signed digit is used to implement constant complex multiplications with a CSA tree for lower power and cost. The simulation shows the module can reach low cost/spl bsol/power and high speed for OFDM-based high-speed wireless applications.