An asynchronous data-path design for Viterbi decoder

A novel asynchronous data-path design is described. Circuits for the asynchronous adder unit, asynchronous comparator unit, and asynchronous selector unit are proposed. An asynchronous data-path ACS (add-compare-select) for a Viterbi decoder is formed. The performance of the 4-bit ACS is analyzed with a novel method based on a multi-delay model. The results of performance analysis of the asynchronous 4-bit ACS show that the average case response time of 6.81 ns is only 84% of the worst-case response time, 8.08 ns. It reveals that the asynchronous data-path has some performance advantages over the synchronous one.