Cart (Loading....) | Create Account
Close category search window
 

A novel LOP to improve the normalization of the FP adder in DSPs

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Fang Jianping ; Inst. of Microelectron., Xidian Univ., China ; Hao Yue ; Che DeLiang

This paper presents a novel leading-one predictor (LOP) for an SMDSP extended precision floating-point adder in digital signal processors (DSPs.). The LOP is area-efficient and has less delay overhead. The regular circuit architecture also makes it easy to design and implement in VLSI. In this paper, we mainly describe the structural and logical design of the LOP module that can be applicable to many floating-point adders.

Published in:

Solid-State and Integrated Circuits Technology, 2004. Proceedings. 7th International Conference on  (Volume:3 )

Date of Conference:

18-21 Oct. 2004

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.