A novel LOP to improve the normalization of the FP adder in DSPs

This paper presents a novel leading-one predictor (LOP) for an SMDSP extended precision floating-point adder in digital signal processors (DSPs.). The LOP is area-efficient and has less delay overhead. The regular circuit architecture also makes it easy to design and implement in VLSI. In this paper, we mainly describe the structural and logical design of the LOP module that can be applicable to many floating-point adders.