VLSI implementation of full pixel motion estimation processor for MPEG-4 AS profile

Efficient 1D and 2D mixed motion estimation array architectures for MPEG-4 AS profile video encoding are presented in this paper. To reduce the utilization of the global bus to the external memory and to improve the computation efficiency of the array, a novel local memory scheme and an improved 2D systolic array architecture for 16/spl times/16 macroblock motion estimation are proposed. For 8/spl times/8 block motion estimation, a 1D broadcast array architecture is also presented. The motion estimation processor is implemented using TSMC 0.25 /spl mu/m 1-poly 5-metal CMOS technology, which occupies a silicon area of 3.19/spl times/3.19mm/sup 2/. Experimental results show that it is able to estimate texture motion vectors of MPEG-4 AS profile in ITU-R601 format (720/spl times/576 at 25 Hz/PAL) in real-time at around 93.7 MHz.