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This paper describes a background (BG) optimization method for a phase-locked loop (PLL) by changing the circuit parameters of the PLL circuits. Measuring the phase shift of the voltage-controlled oscillator (VCO) at each input reference clock, we can determine the phase jitter performance with accuracy equal to a time interval analyzer (TIA). Using the combination of the global optimization method at initial stage and the local optimization method for the background calibration always gives the PLL the smallest jitter performance under process variation, supply voltage modulation, and temperature variation. The test environment fabricated by the 0.15-μm CMOS controlled by an external FPGA demonstrates enough ability to suppress the impacts of the environmental variations.
Date of Publication: April 2005