Referenced Items are not available for this document.
In a 0.13-μm CMOS logic compatible process, a 256K × 32 bit (8 Mb) local SONOS embedded flash EEPROM was implemented using the ATD-assisted current sense amplifier (AACSA) for 0.9 V (0.7 ∼ 1.4 V) low VCC application. Read operation is performed at a high frequency of 66 MHz and shows a low current of typically 5 mA at 66-MHz operating frequency. Program operation is performed for common source array with wide I/Os (×32) by using the data-dependent source bias control scheme (DDSBCS). This novel local SONOS embedded flash EEPROM core has the cell size of 0.276 μm2 (16.3 F2/bit) and the program and erase time of 20 μs and 20 ms, respectively.
Published in:
Solid-State Circuits, IEEE Journal of
(Volume:40
,
Issue:
4
)
Date of Publication: April 2005
- Page(s):
- 877 - 883
- ISSN :
- 0018-9200
- INSPEC Accession Number:
- 8397741
- Digital Object Identifier :
- 10.1109/JSSC.2005.845564
- Date of Current Version :
- 25 April 2005
- Issue Date :
- April 2005
- Sponsored by :
- IEEE Solid-State Circuits Society
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