Referenced Items are not available for this document.
A new VLSI architecture using free discrepancy Berlekamp-Massey (FDBM) algorithm is proposed for wireless applications. Firstly, this project uses the FDBM algorithm to reduce the path delay. A method of module reuse is applied to reduce the overall core size successfully. Using single system clock, it is easy to integrate the core into SoC. As a result, this RS decoder has reduced core size and performs in low power with simple system integration.
Published in:
Circuits and Systems, 2004. Proceedings. The 2004 IEEE Asia-Pacific Conference on
(Volume:2
)
Date of Conference: 6-9 Dec. 2004
- Page(s):
- 1069 - 1072 vol.2
- Print ISBN:
- 0-7803-8660-4
- INSPEC Accession Number:
- 8315645
- Digital Object Identifier :
- 10.1109/APCCAS.2004.1413068
- Product Type:
- Conference Publications
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