By Topic

The design of RS decoder with a small core for portable communication

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Jing, M.-H. ; Coll. of Electr. & Inf. Eng., I-Shou Univ., Kaohsiung, Taiwan ; Truong, T.K. ; Chen, Y.H. ; Luo, Y.C.

A new VLSI architecture using free discrepancy Berlekamp-Massey (FDBM) algorithm is proposed for wireless applications. Firstly, this project uses the FDBM algorithm to reduce the path delay. A method of module reuse is applied to reduce the overall core size successfully. Using single system clock, it is easy to integrate the core into SoC. As a result, this RS decoder has reduced core size and performs in low power with simple system integration.

Published in:

Circuits and Systems, 2004. Proceedings. The 2004 IEEE Asia-Pacific Conference on  (Volume:2 )

Date of Conference:

6-9 Dec. 2004