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Realization of a systematic bit-wise decomposition metric

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3 Author(s)
Chia-Wei Chang ; Dept. of Commun. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan ; Po-Ning Chen ; Han, Y.S.

A realization structure for our previously proposed systematic recursive formula for bit-wise decomposition of M-ary symbol metric is proposed, which can be applied to reduce the memory space and processing latency of a system where the information sequence is binary-coded and interleaved before M-ary modulated. Different from conventional structure where de-interleaver and decoder are separate circuits, our structure de-interleaves and decodes at the same time.

Published in:

Circuits and Systems, 2004. Proceedings. The 2004 IEEE Asia-Pacific Conference on  (Volume:2 )

Date of Conference:

6-9 Dec. 2004