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POMR: a power-aware interconnect optimization methodology

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3 Author(s)
A. Youssef ; Dept. of Electr. & Comput. Eng., Univ. of Waterloo, Ont., Canada ; M. Anis ; M. Elmasry

As VLSI technologies scale down, the average die size is expected to remain constant or to slightly increase with each generation. This results in an average increase in the global interconnect lengths. To mitigate their impact, buffer insertion has become the most widely used technique. However, unconstrained buffering is expected to require several hundreds of thousands of global interconnect buffers. This increased number of buffers is destined to adversely impact the chip power consumption. In this paper, an optimal power maze routing and buffer insertion/sizing problem for a two-pin net is formulated, as a shortest paths ranking problem. The pseudopolynomial time bound of the new formulation fits well within the context of the increased number of buffers. In fact, power savings as high as 25% for the 130-nm technology with a 10% sacrifice in delay is achieved. Furthermore, with the advent of dual threshold technologies, power sensitive applications can substantially benefit from adopting dual threshold buffers. Accordingly, the proposed problem formulation is extended to incorporate the selection of the buffer threshold voltage, where a twofold increase in power savings is observed. During the assessment of the impact of technology scaling using a set of MCNC Benchmarks, an average power saving as high as 35% with a 10% sacrifice in delay is observed. In addition, there is a 10% variation in the power savings when accounting for the process variations.

Published in:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems  (Volume:13 ,  Issue: 3 )