Skip to Main Content
Surfing is a latchless pipelining technique where the propagation delays of gates and other logic functions are modulated to produce event attractors. We describe a test chip that demonstrates a surfing pipeline ring and then introduce new circuits that dramatically reduce the energy overhead for surfing. Our test chip implements a twelve-stage, surfing ring that supports two independent waves of computation without latches or other storage elements. We have operated the chip for over 48 hours and more than 2.6×1015 surfing events without an error. However, the energy consumption of the ring is unacceptable for scaling to larger applications. Thus, we introduce a new family of surfing circuits that use less energy than their domino counterparts and provide a factor of up to 1.75 improvement by the Et2 metric. We demonstrate this new family with the design of a carry lookahead adder.