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Coarsely integrated operand scanning (CIOS) architecture for high-speed Montgomery modular multiplication

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3 Author(s)
McLoone, M. ; Inst. of Electron., Commun. & Inf. Technol., Queen''s Univ. Belfast, UK ; McIvor, C. ; McCanny, J.V.

A generic coarsely integrated operand scanning (CIOS) architecture that provides high speed Montgomery modular multiplication is presented in This work. The architecture is capable of supporting varying operand sizes. It achieves a throughput of 210 Mbps, 289 Mbps and 334 Mbps for 128-bit, 256-bit and 512-bit operand sizes respectively, when implemented on a Virtex XC2 VP50 FPGA. Throughputs of up to 400 Mbps are achieved if the final subtraction in the Montgomery algorithm is excluded. To the authors' knowledge this is the fastest Montgomery multiplication architecture reported in the literature.

Published in:

Field-Programmable Technology, 2004. Proceedings. 2004 IEEE International Conference on

Date of Conference:

6-8 Dec. 2004