By Topic

Multiplexing schemes for cost-effective fault-tolerance

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Roy, S. ; Sch. of Electr. Eng. & Comput. Sci., Washington State Univ., Pullman, WA, USA ; Beiu, V.

Motivated by the need for cost-effective fault-tolerant nano architectures, we explore von Neumann multiplexing (vN-MUX) at small and very small redundancy factors. We present a novel analysis of vN-MUX of 3-input majority gates (MAJ-3), using combinatorial arguments to exactly determine performance. We show that MAJ-3 vN-MUX performs very well when compared to other redundancy schemes, increasing the allowed device error probability by four orders of magnitude (for small redundancy factors). We describe in detail an extension, called MAJ-3 vN-MUX(N,k), that contributes up to four more orders of magnitude, by excluding superfluous restorative stages for very small redundancy factors. We also analytically determine the performance of MAJ-3 vN-MUX for large redundancy factors, finding that the maximum tolerable gate failure probability is 0.0197 (in contrast to 0.0107 for NAND-2 vN-MUX).

Published in:

Nanotechnology, 2004. 4th IEEE Conference on

Date of Conference:

16-19 Aug. 2004