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On single electron technology full adders

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2 Author(s)
M. Sulieman ; Sch. of EE&CS, Washington State Univ., Pullman, WA, USA ; V. Beiu

This paper reviews several full adder (FA) designs in single electron technology (SET). In addition to the structure and size already reported for these SET FAs, this paper provides a quantitative and qualitative comparison in terms of delay, power dissipation, and sensitivity to (process) variations - for the first time. This can allow for a better understanding of the advantages and disadvantages of each solution. A new SET FA design, based on capacitive SET threshold logic gates, is described and compared with the other SET FAs.

Published in:

Nanotechnology, 2004. 4th IEEE Conference on

Date of Conference:

16-19 Aug. 2004