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We present the results of measurements of thermal resistivity of the heterojunction bipolar transistor (HBT) devices, utilizing selective ion implantation to define the subcollector. This new device fabrication technique resulted in high-speed HBT devices with substantially reduced thermal resistivity, compared to devices utilizing the conventional fabrication approach which includes mesa isolation for pattern definition. The measurements were taken on full-thickness 3" InP wafers at Tamb from 30°C to 180°C and two separate emitter current densities. We present data on three device epitaxial structures with identical device layouts and discuss the relationship of Vbe to temperature at these elevated power and temperature levels.