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With high-speed computation now driving with clock rates in the tens of gigahertz, changes have to be made to thermal management and packaging to respond to the increasing power density in such systems. The authors describe one successful approach to a subnanosecond cycle time supercomputer design. Thermal measurements and modeling prove that this design is scalable to power dissipation levels as high as 25 kW, while still achieving the subnanosecond cycle times that were originally targeted. To the authors' knowledge, this is the first time a true three-dimensional electronic interconnected spray cooled thermal management scheme using polycrystalline diamond to handle the extraordinary heat loads has been described and demonstrated at these power levels.
Device and Materials Reliability, IEEE Transactions on (Volume:4 , Issue: 4 )
Date of Publication: Dec. 2004