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High-reliability programmable CMOS WTA/LTA circuit of O(N) complexity using a single comparator

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2 Author(s)
Hung, Y.-C. ; Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan ; Liu, B.-D.

A high reliability complementary metal-oxide-semiconductor (CMOS) winner-takes-all/loser-takes-all circuit of O(N) complexity with programmable capability is designed. Based on the proposed architecture, the precision of the circuit is independent of the number of inputs. This circuit is easily programmed for WTA or LTA function by an enable signal, without modifying the circuit structure or preprocessing the input variables. Since the circuit contains only simple logic gates and a single comparator, it is tolerant of VLSI process variations. The response time of the circuit increases linearly with the number of inputs. The input signal range of the circuit allows rail-to-rail (0-VDD) operation. The supply voltage ranges from 2.7 V to 5 V. An experimental chip with six inputs was fabricated using 0.5-μm CMOS double-poly double-metal technology. The results show that a cell is either a winner or a loser if its input voltage is larger or smaller than the other cells by 10 mV.

Published in:

Circuits, Devices and Systems, IEE Proceedings -  (Volume:151 ,  Issue: 6 )