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The demand for higher functionality and higher performance at lower cost is the main motivation behind the continuous downsizing of CMOS based ICs. The feature size of individual transistor is shrinking from deep sub-micrometer (DSM) to even nanometer region. As the scale of integration improves, more transistors, faster and smaller than their predecessors, are being packed into a chip. This leads to the steady growth of the operating frequency and processing capacity per chip, resulting in increased power dissipation. A need for low-power VLSI chips arises from such evolutionary forces of integration on circuits. The craving for smaller, lighter and more durable electronic products and the increased market demand for portable consumer electronics powered by batteries, translate to low power requirements. Low-power CMOS VLSIs find increasing applications in notebook computers, digital personal communication services having portable multimedia terminals with voice and handwriting recognition facilities. Design of DSM CMOS and its downsizing keeping at the same time power consumption at a manageable level requires deep understanding of the physics involved. The hot carrier effects, velocity saturation and overshoot, impact ionization, DIBL, GIDL, punch through, tunneling effects and hot carrier injection through thin gate play important roles in the design of low power devices and also provide a guideline for further scaling of feature size and control of power level. In addition quantum mechanical effects induce a threshold shift and depth of inversion layer. All the present simulation tools need modification to take into account all the effects. Alternate devices like SiGe HFETs and CMOS on silicon on insulator are in the process of evolution. The aim of the tutorial is to cover the basic physics involved in DSM and nanometer sized CMOS ICs, technologies involved and the modeling techniques for low power CMOS and emerging devices.