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Tutorial: Power-aware, reliable microprocessor design

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1 Author(s)
Bose, P. ; IBM T.J. Watson Res. Center, Yorktown Heights, NY, USA

Summary form only given. In this tutorial, we present the foundational principles and methodologies behind the design of power-efficient, reliable microprocessors. The stress is on early-stage (pre-RTL) definition at the micro-architecture level, although relevant details from lower levels of design (e.g. logic, circuits and below) are also covered where appropriate. We first cover the topic of pre-silicon modeling to estimate performance, power, temperature and reliability, in the context of target workloads of interest to the design team. We then delve into the definition of the optimal pipeline depth for a microprocessor: a task that is one of the basic initial decisions faced by the design team. Subsequently, we cover the topic of adaptive micro-architectures: those that are designed to change with variations in the workload, with the goal of maximizing power-performance efficiency, reliability, or both. We address both active (or dynamic) and passive (or static) power in presenting evaluations of various micro-architectural techniques for power management.

Published in:

VLSI Design, 2005. 18th International Conference on

Date of Conference:

3-7 Jan. 2005