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Implementation of a large scale hardware neural network system based on stochastic logic

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4 Author(s)
A. Momoi ; Res. Inst. of Electr. Commun., Tohoku Univ., Sendai, Japan ; S. Akimoto ; S. Sato ; K. Nakajima

We present a large scale hardware neural network system which consists of 16 chips, 1024 neurons. The system is realized by using stochastic logic. Stochastic logic makes possible to implement numerous neurons on a VLSI chip and to build a system comprising multiple chips easily. In addition, stochastic logic has a characteristic as some noise is generated while coding operations. This noise is effective for escaping from the local minima in a Hopfield network. The availability of this noise is confirmed in the measurement of our system.

Published in:

Neural Networks, 2004. Proceedings. 2004 IEEE International Joint Conference on  (Volume:4 )

Date of Conference:

25-29 July 2004