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This paper is dealing with the design of a library of basic building cells for an "integrate & fire" or "spiking" neural network hardware implementation. Each cell of this library consists of transistor level schematic, mathematics model for fast system level simulations, abstracted layout for automatic layout generation and fully checked layout of the cell. The main cells: neuron and a synapse were designed according to their biological counterparts conceptually as close as possible to better mimic the real neural networks. The switched capacitor design technique was involved in the main cells to save the design area. Using this library a test chip was designed and produced and at the end of this paper few measurements are described and shown.
Neural Networks, 2004. Proceedings. 2004 IEEE International Joint Conference on (Volume:4 )
Date of Conference: 25-29 July 2004