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Practical measurement of timing jitter contributed by a clock-and-data recovery circuit

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2 Author(s)
Pease, C. ; Nat. Semicond. Corp., Santa Clara, CA, USA ; Babic, D.

This paper describes a measurement of high-frequency jitter contributed by a clock-and-data recovery circuit. The contributed jitter is expressed with deterministic and random jitter terms and is given for a specific bit sequence. The measurement is illustrated on two multichannel CMOS serializer/deserializer chips applicable to 10-G Ethernet, 10-G Fibre Channel, and InfiniBand at per-channel rates of 2.5 and 3.125 GBaud.

Published in:

Circuits and Systems I: Regular Papers, IEEE Transactions on  (Volume:52 ,  Issue: 1 )

Date of Publication:

Jan. 2005

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