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The use of bang-bang phase-locked loops (BBPLLs) has become increasingly common in a lot of communications systems, in particular in the area of clock and data recovery. Although most of the BBPLLs implemented up to now use analog loop filters, the binary output of the phase detector naturally lends itself to a digital implementation. In this paper, the nonlinear dynamics of first- and second-order digital BBPLLs is analyzed from a design perspective. In particular, the effects of loop delays on the PLL performances are emphasized. Conditions for the existence of orbits (limit cycles) are derived, and the timing jitter performances are evaluated. Finally, useful expressions for the design and optimization of the PLL parameters for low jitter are given.